Overvoltage protection devices, or surge protection devices, have been highly developed for protecting electrical equipment, especially semiconductor circuits, from damage due to dangerous voltage transients. Voltage transients occurring on conductors, such as communication lines, may be caused by lightning strikes, by electrostatic discharges, electromagnetic fields, etc. Overvoltage protection devices have typically included four layer semiconductor devices, namely thyristors. Ideally, an overvoltage protection device should respond very rapidly to suppress high speed transient voltages with very little overshoot, have a very high current-carrying capability, and exhibit very little capacitance.
One overvoltage protection device that has experienced widespread use is a two-terminal thyristor that employs four semiconductor layers and buried regions to facilitate and control turn on of the device in response to transient voltages. Such devices are known as Sidactor® overvoltage protection devices which are supplied by Littelfuse, Inc., Des Plaines, Ill., under the brand name of Teccor®. The incorporation of buried regions into an overvoltage protection device is disclosed in U.S. Pat. No. 5,479,031 by Webb et al; U.S. Pat. No. 6,084,253 by Turner, Jr.; U.S. Pat. No. 6,531,717 by Casey, et al; and U.S. Pat. No. 6,956,248 by Casey et al.
The buried regions in a thyristor device determine, or at least significantly affect, many operating parameters of the device. The number and placement of the buried regions affect the turn on response of the device. The impurity concentration of the buried regions determine the breakover voltage of the thyristor device, i.e., the voltage at which the device enters a low impedance negative resistance region. The higher the impurity concentration in the buried regions, the lower the breakover voltage of the device. Typically, the buried regions are formed by depositing a high concentration of a dopant on the surface of the wafer for a long period of time, such as 30 hours, and then driving the dopant into the wafer for another 30 hours. A high temperature and long term schedule is required to drive the dopants deeply into the wafer. Once the buried regions are formed, a base region is formed thereover, and the emitter or cathode region is formed in the base region, again at standard elevated semiconductor processing temperatures.
FIG. 1 illustrates the detailed construction of a unidirectional surge protection device 8 fabricated according to prior art techniques. The device 8 is formed in the top surface of a P-type silicon substrate 10, which is shown between metal contacts 26 and 28. Semiconductor region 12 is in the middle of the semiconductor substrate 10 and defines both the mid-region of the four layer thyristor, and the base of a PNP transistor. A first N-type base region 14 is formed in the top surface of the substrate 10, and a second N-type anode region 16 is formed in the bottom surface of the substrate 10. However, plural heavily doped buried regions 18 are formed in the mid-region 12, by standard semiconductor diffusion techniques, before either base region 14 or 16 is formed. The buried regions 18 are formed by depositing boron ions for about three days, resulting in a saturation concentration of about 1019 atoms per cm3 on the surface of the substrate 10, and a depth of about 80 microns. This impurity concentration is effective to provide a breakover voltage in the range of about 8-12 volts. The wafer undergoes a diffusion process at a temperature of about 1275° C. for about three days to activate the boron ions. After activation of the boron ions, both sides of the semiconductor substrate 10 are subjected to another diffusion process in which the N-type base region 14 and the anode region 16 are formed. The concentration of the N-type impurity must be sufficient to compensate the P-type boron in the buried regions 18. As a result, junctions 20 are formed between the base region 14 and the buried regions 18. It is this junction 20 that determines the breakover voltage of the device. The avalanche breakdown of the junction provides a negative resistance characteristic to the device. A P-type emitter 22, with holes therein defining shorting dots 24, is formed in the base region 14. The shorting dots 24 in the emitter 22 can be formed over the buried regions 18 as disclosed in U.S. Pat. No. 5,479,031. Alternatively, the buried regions 18 can be fully offset from the emitter edges as disclosed in U.S. Pat. No. 6,531,717. A metal emitter contact 26 is formed in electrical contact with both the shorting dots 24 of the base region 14 and the emitter 22. An anode metal contact 28 is formed on the bottom of the chip in electrical contact with the anode region 16.
While the foregoing is time consuming, and thus expensive, it represents the conventionally accepted method of fabricating two-terminal thyristors, of the Sidactor overvoltage protection device type. One disadvantage of the foregoing method of forming buried regions is that such regions cannot generally be made with a small area, and thus with a small capacitance, as the high temperature processing steps cause the impurities to diffuse outwardly in all directions in the wafer. Thus, the deeper the buried regions are formed, the larger they grow as a function of time and temperature. As the chip undergoes high temperature processing, the impurities in the buried regions diffuse outwardly, thus reducing the concentration of the impurity. The reduction in the impurity concentration of the buried regions correspondingly increases the breakover voltage of the device. Tight control over the breakover voltage is thus difficult to achieve. When the buried regions form large-area junctions with the base region of the chip, the capacitance of such device is correspondingly large. Large, capacitance thyristors may be suitable for some applications, but not in high speed data transmission applications, such as in DSL, VDSL or with other high speed communication line transmission protocols.
An additional concern is that if low voltage overvoltage protection devices are required, such as for digital transmission lines, then the buried regions must have high concentration impurity levels to lower the reverse breakdown voltage of the junctions associated with the buried regions. Again, it becomes more difficult to achieve high concentration levels in the regions deeply buried in the semiconductor chip, as there is a limit as to the concentration of the dopant deposited on the surface of the chip. In many instances, the concentration of the impurities deposited on the surface of the semiconductor substrate to form the buried regions is at a saturation level, for low voltage operation. Then, as the long diffusion process is carried out to move the dopants deeply into the semiconductor chip, the concentration of the dopant becomes less as a function of distance from the surface of the chip. Accordingly, it is difficult and costly to fabricate overvoltage protection devices that have low breakover voltages useful in protecting digital and other low voltage lines.
From the foregoing, it can be seen that a need exists for a process and corresponding product that allows deep buried regions to be formed so that low capacitance, low voltage surge protector devices can be efficiently fabricated. A need also exists for a low capacitance surge protection device for use with high speed communication lines so that the high speed signals are not adversely affected. An additional need exists for a method of forming buried regions in a surge protection device so that a high degree of control can be achieved over the breakover voltage of the device.